Dual Adjustable Clock Divider
Instructions for Use and Change Log
Tank Profane, Tsyklon Labs

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Instructions for Use (Note: The function of Channel 2 is identical to Channel 1)
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POT 1 - Clk1 Div - Channel 1 Clock Divisor
// Value Range: 1 through 10
// This potentiometer selects how many input Trigger Pulses to count before generating an Output Pulse
	(e.g. - a value of 1 generates an Output Pulse for every Trigger, a value of 2 generates an Output Pulse
	for every other Trigger, and a value of 3 generates and Output Pulse, then waits two more Trigger Pulses
	before generating the next Output Pulse.)

SW 1 - INV/NRM/OFF - Channel 1 Output is Inverted, Normal, or Off
// Value Range: Up = Inverted, Middle = Normal, Down = Off
// This switch selects the mode for the Outputs Pulses. In Normal mode, the Output Pulses have the same rising
	and falling edges as the Trigger Pulses. In Inverted mode, the Output Pulses have rising and falling edges
	that are the opposite direction of the Trigger Pulses. In Off mode, Channel 1 will not generate any Output Pulses.

DIG IN 1 - Trigger - Trigger Pulse Inputs for Channels 1 and 2
// Value Range: ON/OFF
// This digital input is used to provide clock pulses for the Clock Divider to divide. Pretty straight forward, no?

DIG IN 2 - Reset - Reset Pulse Inputs for Channels 1 and 2
// Value Range: ON/OFF
// This digital input is used to provide a reset signal for the Clock Divider. While the input is OFF, it is business as usual for
	our Clock Divider. When the input is ON, the Digital Outputs are held in the OFF state.

CV IN 1 - Not used at this time. Future plans are to use it for CV control of Channel 1 Clock Divisor

DIG OUT 1 - Clk 1 - Channel 1 Divided Output Pulses
// Value Range: ON/OFF
// This digital output is where we see the results of all of the selections made above at POT 1 and SW 1.

CV OUT 1 - Not used at this time. Ideas for any future use are appreciated.

NOTES: During testing, it became evident that this particular Arduino board really needs at least a 5VDC
	Trigger and Reset signals in order for the sketch to do anything. Both Digital Outputs will generate
	5VDC pulses.

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Change Log
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v0.4 - 8 Dec, 2014
- Reset input clears pulse counts and keeps digital outputs low
- added function for each switch for inv/nrm/off control

v0.3 - 7 Dec, 2014
- Divisor calculations work for
- Logic for incrementing pulse counts for each divider on positive transition of Trigger input
- finish logic that generates output pulse on clock transition 1 and stays low for remainder of counts
- fix issues with single pulse divisor (in essence, pass trigger signal) not matching the duty cycle of the Trigger
- duplicated logic from channel 1 to channel 2

v0.1 - 6 Dec, 2014
- No new functionality for clock output
- testing and scaling function of Potentiometer 1 input
- serial monitor working for debugging

v0.0 - 5 Dec, 2014
- 5v square clock signal that is applied to Digital Input 1 is passed successfully to Digital Output 1
- humble start, but IDE and Download Cable both work